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Prof. Ankur Srivastava |
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ECE Assistant Professor Ankur Srivastava was featured in EE Times for his paper, "Variability-Driven Formulation for Simultaneous Gate Sizing and Post-Silicon Tunability Allocation," for which he recently earned a best paper award at the ACM International Symposium on Physical Design (ISPD 2007).
The paper, authored by Srivastava and his graduate student advisee, Vishal Khandelwal, proposes the use of tunable clock buffers in computer chips that could be used to fix specification violation problems that arise after silicon is manufactured due to fabrication randomness. This process could prove to be a very important milestone in the design and fabrication process of micro and nanoscale chips, offering the novel approach of integrating both post-silicon and pre-silicon optimizations into one flow.
Srivastava explains that the paper is aimed at finding the "optimal balancing point" between post-silicon tuning and statistical optimization during the design process. The paper underscores the importance of tying pre-fabrication strategies to post-fabrication optimization in achieving efficiency in the design and manufacturing process.
For more information about this significant paper, read the EE Times story online at: http://www.eetimes.com/news/design/showArticle.jhtml?articleID=198100044.
The ISPD provides a forum to exchange ideas and promote research on critical areas related to the physical design of VLSI systems. For more information about the symposium, visit: http://www.ispd.cc/.
March 22, 2007
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