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![Gang Qu presenting the keynote address at the IEEE Asian Test Symposium. Photo credit: ATS. [Click the photo for a full-size image]](http://mnemosyne.umd.edu/tomcat/newsengine/articleImg/article15842.large.jpg)
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Gang Qu presenting the keynote address at the IEEE Asian Test Symposium. Photo credit: ATS. [Click the photo for a full-size image] |
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On Oct. 15, 2023, Professor Gang Qu (ECE/ISR) delivered a keynote speech, "Towards Building Secure Scan-based DfT," at the 32nd IEEE Asian Test Symposium (ATS) in Beijing, China. ATS is an international forum for world engineers and researchers (not just those from Asia), to present and discuss system, board and device testing with design, manufacturing and field considerations in mind. Recently, hardware security has attracted a lot of attention in the testing community.
VLSI (Very Large Scale Integration) chip testing has been a challenge with equal importance of chip design for many decades. Scan chain-based DfT (design for test) technology allows test engineers to access and control chip's internal states for testing purposes and significantly improves test coverage and efficiency. It is an important part of IEEE Standard 1149.1 (1990) and is used by semiconductor chip manufacturers to provide various vendor-specific features.
However, scan-based DfT also creates security vulnerabilities ranging from leaking sensitive information (such as cryptographic keys) to allowing an attacker to gain access and control of internal states during the chip's execution.
In his keynote, Dr. Qu introduced scan chain technology and security attacks using scan chain as a side channel. He then focused on current research advances that not only help in building secure scan chains but also enhance chip security by leveraging scan chains.
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October 20, 2023
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